-- cache tempalte
-- this is provided as a guide to build your cache. It is by no means unfallable.
-- you may need to update vector bit ranges to match specifications in lab handout.
--
-- THIS IS NOT ERROR FREE CODE, YOU MUST UPDATE AND VERIFY SANITY OF LOGIC/INTERFACES
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity cache_ctrl is
	port(
		CLK					:	in	std_logic;
		nReset			:	in	std_logic;
		Hit					:	in	std_logic;
		Read				:	in	std_logic;
		Write				:	in	std_logic;
		RamWait			:	in	std_logic;
		RamState		:	in	std_logic_vector (01 downto 0);
		BlockAddr		:	in	std_logic_vector (28 downto 0);
		RamWord			:	in	std_logic_vector (31 downto 0);
		CPUWord			:	in	std_logic_vector (31 downto 0);
		BlockDirty	:	in	std_logic;
		CacheBlockI	:	in	std_logic_vector (63 downto 0);
		CacheBlockO	:	out	std_logic_vector (63 downto 0);
		WordAddr		:	out	std_logic_vector (31 downto 0);
		RamRead			:	out	std_logic;
		RamWrite		:	out	std_logic;
		WrEn				:	out	std_logic	
	);
end cache_ctrl;

architecture struct of cache_ctrl is 
-- setup data types here i.e. state
begin

cctrl_state: process(CLK, nReset)
begin
	if nReset = '0' then
		-- set state to idle
	elsif rising_edge(CLK) then
		-- set state to next state
	end if;
end process cctrl_state;

cctrl_ns: process(FILL_ME_IN);
begin
	case state is
		-- read data from memory to fill cache block
		-- write data from cache block to memory when dirty
	end case;
end process cctrl_ns;

end;

